Cyclorama Hardware & Programmer's Reference

1 System overview

The Avenell Cyclorama is a cartridge games console built around three custom chips: the Tally processor (AV-1601), the Barndoor video chip (AV-2210) and the Cue audio chip (AV-3105). A single crystal clocks all three, so every event in the machine happens at an exact, repeatable time. This chapter introduces the parts and the rules they share: clocks, timing, the memory map and the notation used throughout the manual.

1.1 The Cyclorama at a glance

1.2 Block diagram

1.3 Clocks and timing

One crystal oscillator at 945/44 MHz, about 21.477 MHz, is the master clock. This manual counts time in master cycles, written M. Every other clock is an integer division of it:

A scan line is 1368 master cycles per line = 342 dots = 228 CPU cycles. A frame is 262 lines per frame, of which lines 0–223 are the 224 visible lines and lines 224–261 are vertical blank. Within a line, dots 0–255 are output as pixels and dots 256–341 are horizontal blank. A frame is 358,416 master cycles = 59,736 CPU cycles per frame, so the Cyclorama produces about 59.9228 frames per second.

Active display means dots 0–255 of lines 0–223. Some operations (access to the video data ports, DMA) are slower during active display; see §2.6 Cycle counts.

Events at fixed positions in the frame:

1.4 The reference timing model

All Cyclorama hardware is synchronous to the master clock and fully deterministic: given the same ROM image, the same initial cartridge-RAM contents and the same controller samples on each frame, it produces exactly the same picture, sound and memory contents every time. (On a real console the volatile memories power up in an undefined state; the reference model starts them at zero.) Avenell's reference model of the machine, used by the conformance tests, follows these rules, and software may rely on them:

1. Machine state is integer-only. Nothing outside the machine (time of day, randomness) affects it. The only inputs are the ROM image, the initial cartridge-RAM contents and the controller samples taken once per frame (§7.2 Sampling).
2. The processor executes whole instructions. An instruction's cycles complete before any event at a later master-cycle time is observed. An event due at exactly the master cycle at which an instruction starts happens first: the instruction sees its result, and its own register accesses come after it. Such an event is also processed before that boundary's interrupt check, so an interrupt it requests can be taken there: the VBLANK request made at dot 0 of line 224 is taken before the instruction that would have started at that moment, if I = 1 and IE bit 0 is set. (This matters because dot 0 of every line falls on a CPU-cycle boundary: a line is exactly 228 CPU cycles.)
3. All I/O register reads and writes made by an instruction take effect at the master-cycle time at which the instruction starts. This includes every bus access the instruction makes: its instruction fetches and stack accesses as well as its data accesses (§2.2 Memory access). Interrupt entry is timed like an instruction: its two pushes take effect at the master-cycle time at which the entry starts, and any port wait they incur is judged at that time (§3.4 Interrupts).
4. A frame runs from dot 0 of line 0 to dot 0 of line 0 of the next frame, 358,416 M. Frame boundaries are fixed: the picture always starts a new frame every 358,416 M. An instruction that straddles the boundary completes, and its excess cycles are charged to the processor in the following frame, so the processor begins that frame's work slightly later; the video does not move.

1.5 Memory map

The Tally processor addresses 64 KiB, byte by byte. Words are little-endian: the low byte is at the even address.

Writes to ROM are ignored. Every I/O register is 16 bits wide at an even address; byte access is described in §3.7 Byte access to I/O registers. The complete register list is in the register summary appendix, Appendix F I/O register summary.

The Barndoor chip's memories are not in this map. VRAM (32 KiB), OAM (512 bytes) and CRAM (512 entries) are reached only through the port registers VADDR/VDATA, OAMADDR/OAMDATA and CRAMADDR/CRAMDATA, or by DMA.

1.6 Conventions used in this manual

Numbers

Addresses, encodings and register values in tables and prose are hexadecimal and written without a prefix, in four digits: C000, F0DA. Counts, sizes and cycle numbers are decimal. In assembler source, hexadecimal is written $1F or 0x1F and binary %1010.

Bits

Bit 0 is the least significant bit. "Bits 9–0" is a field from bit 9 down to bit 0. A signed n-bit field is two's complement.

Sizes

1 KiB = 1024 bytes; 1 MiB = 1024 KiB. A word is 16 bits.

Access

R: readable; W: writable; R/W: both.

Reserved

A reserved field or encoding has no function now. Software writes 0 to reserved bits and never uses reserved encodings, so that its behaviour is fixed on every Cyclorama.

Undefined

Undefined values may differ between consoles and between power-ons. Software must not depend on them.

2 The Tally processor

Tally (part AV-1601) is Avenell's own 16-bit processor, named after the red lamp that tells a camera crew which camera is live. It has eight fully orthogonal general registers, a separate stack pointer, a byte-addressed 64 KiB address space and a regular instruction set in which every instruction is one 16-bit word, optionally followed by one 16-bit extension word. This chapter is a complete description: an engineer can build a compatible processor, or a simulator, from it alone.

2.1 Programming model

The flag register F:

F is saved on the stack by interrupts and TRAP, restored by RTI, and can be read and written whole with GETF and SETF.

2.2 Memory access

• The address space is byte-addressed and little-endian: the word at address a has its low byte at a and its high byte at a + 1.
• Word accesses ignore address bit 0. A word access to an odd address a reads or writes the word at a & FFFE. Every load of PC (reset, jumps, calls, returns, table jumps, interrupt and TRAP entry) clears bit 0, so instructions are always fetched from even addresses and every return address pushed is even.
• Byte loads (LDB) zero-extend the byte into the register. Byte stores (STB) change exactly one byte of RAM.
• Address arithmetic wraps at 16 bits: FFFE + 4 = 0002.
• Every bus access — an instruction word fetch, an extension word fetch, a data read or a data write — takes 2 CPU cycles. The cycle counts in this chapter are totals that include every access.
• Instruction fetches, extension fetches, stack pushes and pops (PUSH, POP, PUSHM, POPM, CALL, BSR, RTS, RTI, TRAP) and the pushes of interrupt entry are ordinary bus accesses. If one of them addresses an I/O register it has the same side effects and wait cycles as a data access to that register: a fetch from VDATA advances VADDR, and a POP from VSTAT clears its overflow bit. The accesses of an instruction happen in program order: its fetches first, then its data accesses in the order its operation performs them. No sensible program does this, but the result is defined.

2.3 Flag conventions

Every instruction's effect on the flags is listed in the instruction reference. The rules are uniform:

Because C is a borrow after subtraction, the unsigned conditions read naturally: after CMP R0, R1, BLO (C = 1) branches when R0 < R1 and BHS (C = 0) when R0 ≥ R1. The assembler also accepts BCS and BCC for these.

Two's complement overflow V is 1 when the true signed result of the operation lies outside −32768…32767. For shifts, the count n is the value used by the shift (see the individual instructions); counts are never negative.

2.4 Addressing modes

"next" is always the address of the instruction following the current one, after any extension word.

2.5 Instruction formats

Every instruction is one 16-bit word, stored little-endian, optionally followed by one 16-bit extension word. Bits 15–12 of the first word, the major group, select the format:

Register fields are three bits: 000 = R0 … 111 = R7. ddd is the destination (or, for stores, the register whose value is stored) and sss the source or base register.

An extension word follows the first word in exactly these cases:

• group 2 (ALU with 16-bit immediate): the immediate;
• group 8 with mode 00 ([Rs+d16]) or mode 01 ([abs16]): the displacement or address;
• group B with operation 0 (JMP), 1 (CALL) or 5 (JMPT): the target or table address.

No other instruction, including every reserved encoding, has an extension word. The instruction length therefore depends only on the first word, and a disassembler can always find the next instruction.

Bits marked 0 in a layout but not used by an instruction (for example bits 1–0 of group 1, or the source field of group 2) are must-be-zero bits. The assembler writes 0; the processor ignores them.

2.5.1 Decoding

The following procedure decodes any first word w (the numbers are decimal operation numbers; the tables are in the instruction reference):

major ← w >> 12
0:     op ← (w >> 7) & 31;  d ← (w >> 4) & 7;  imm4 ← w & 15
       op 0–26 as listed under group 0;  op 27–31 reserved
1, 2:  op ← (w >> 8) & 15;  d ← (w >> 5) & 7;  s ← (w >> 2) & 7 (group 1 only)
3:     d ← (w >> 9) & 7;  q ← (w >> 8) & 1 (0 MOVQ, 1 ADDQ);  imm ← sx8(w & 255)
4–7:   byte ← major ≥ 6;  store ← major odd;  d ← (w >> 9) & 7;  s ← (w >> 6) & 7
       disp ← (w & 63) × (byte ? 1 : 2)
8:     d ← (w >> 9) & 7;  s ← (w >> 6) & 7;  byte ← bit 5;  store ← bit 4;  mode ← (w >> 2) & 3
9:     d ← (w >> 9) & 7;  store ← bit 8;  disp ← (w & 255) × 2
A:     cond ← (w >> 8) & 15;  disp ← sx8(w & 255)
B:     op ← (w >> 8) & 15:  0 JMP, 1 CALL, 2 PUSHM (mask = w & 255), 3 POPM (mask),
       4 ADDSP (s8 = w & 255; SP changes by sx8(s8) × 2), 5 JMPT (d ← (w >> 5) & 7);  6–15 reserved
C–F:   reserved

Every one of the 65,536 possible first words decodes to exactly one instruction or to a reserved encoding. The opcode map, §2.16 Opcode map, shows the whole space.

2.6 Cycle counts

Instruction timing is simple and exact. Each bus access costs 2 cycles, and most instructions cost nothing beyond their accesses. A register ALU operation is one fetch (2 cycles); an immediate ALU operation fetches two words (4); a short load fetches one word and reads one (4); a load with an extension word fetches two and reads one (6). The rules:

• Shifts and rotates add one cycle per bit of the count n actually used: n = Rs & 15 for the register form, imm & 15 for the group 2 immediate form, and n = 1…16 for the group 0 form (SHL Rd,#n). A shift with count 0 adds nothing.
• Branches cost more when taken. BRA is always taken.
• PUSHM and POPM cost the base plus one word access per register in the mask.
• WAI costs its base cycles and then as long as it waits.
• Video ports. Each read or write of VDATA, OAMDATA or CRAMDATA made during active display (dots 0–255 of lines 0–223) adds wait cycles, as listed, whether it is a data access, a fetch or a stack access. In blanking the ports run at full speed.
• DMA. Writing DMACTL stops the processor for the whole transfer, 4 + 2 × DMALEN cycles if the transfer starts outside active display, or 4 + 4 × DMALEN if it starts during active display. The stop is in addition to the cycles of the store instruction itself, belongs to that instruction, and interrupts are recognised only after it. The transfer starts at the start time of the store (§1.4 The reference timing model). Only the beam position at the start of the transfer matters: a transfer that starts in vertical blank and runs on into line 0 keeps the lower rate. The DMA channel is described with the video chip, §5.12 DMA and video port timing.
• Interrupt entry takes its own cycles between two instructions (§3.4 Interrupts): 12, plus any port wait cycles its two pushes incur.

With 228 CPU cycles per line, a register ALU operation takes 1/114 of a line; a frame holds room for about 30,000 of them.

2.7 Reading the instruction reference

The reference that follows lists every instruction in encoding order. Each entry gives:

Forms

One row per encoding: the CYASM syntax, the first word as a bit diagram (fixed bits printed 0 or 1, variable fields shaded and named, ignored must-be-zero fields shown grey), the base word (the first word with every variable field 0), the extension word if any, and the cycle count.

Operation

Pseudo-code. ← is assignment; arithmetic is modulo 65536 (16 bits) unless noted; mem16[a] is the word at a & FFFE and mem8[a] the byte at a; sx8(x) sign-extends an 8-bit value to 16 bits; s(x) is the signed (two's complement) value of x; push(x) means SP ← SP − 2 then mem16[SP] ← x; pop() means read mem16[SP] then SP ← SP + 2; next is the address of the following instruction; src is the second operand (Rs, or the immediate).

Flags

* set from the result (Z = result is 0, N = bit 15 of the result); – not affected; 0 cleared; carry unsigned carry out; borrow unsigned borrow; ovf signed overflow; out the last bit shifted out (see the flag conventions for count 0); >FFFF product too large; pop loaded from the stack; Rd loaded from the register.

2.8 Instruction reference

Instructions are grouped by major group, in encoding order.

(none)

halt: no further instructions are fetched until RESET

while (IE & IF) = 0: fetch nothing; time passes
(then the ordinary interrupt check between instructions applies)

PC ← pop()

F ← pop() & 001F
PC ← pop()

I ← 1 (acceptance delayed by one instruction)

I ← 0 (immediately)

push(next)
push(F)
I ← 0
PC ← mem16[0008]

Rd ← Rd XOR FFFF

Rd ← 0 − Rd

Rd ← Rd + 1

Rd ← Rd − 1

Rd ← sx8(Rd & 00FF)

Rd ← Rd & 00FF

Rd ← (Rd << 8 | Rd >> 8) & FFFF

C ← bit (16 − n) of Rd
Rd ← (Rd << n) & FFFF

C ← bit (n − 1) of Rd
Rd ← Rd >> n (zeros enter at bit 15)

C ← bit (n − 1) of s(Rd), where bit 16 and above equal bit 15
Rd ← s(Rd) >> n (copies of bit 15 enter)

Rd ← (Rd << n | Rd >> (16 − n)) & FFFF
C ← bit 0 of the result

PC ← Rd & FFFE

push(next)
PC ← Rd & FFFE

SP ← SP − 2
mem16[SP] ← Rd

Rd ← mem16[SP]
SP ← SP + 2

Rd ← SP

SP ← Rd & FFFE

Rd ← F (bits 15–5 are 0)

F ← Rd & 001F

Rd ← src

r ← Rd + src
C ← 1 if r > FFFF
V ← 1 if s(Rd) + s(src) is outside −32768…32767
Rd ← r & FFFF

r ← Rd + src + C
C ← 1 if r > FFFF
V ← 1 if s(Rd) + s(src) + C is outside −32768…32767
Rd ← r & FFFF

C ← 1 if src > Rd (unsigned borrow)
V ← 1 if s(Rd) − s(src) is outside −32768…32767
Rd ← (Rd − src) & FFFF

C ← 1 if src + C > Rd (unsigned borrow)
V ← 1 if s(Rd) − s(src) − C is outside −32768…32767
Rd ← (Rd − src − C) & FFFF

flags as SUB Rd, src
Rd is not written

Rd ← Rd AND src

Rd ← Rd OR src

Rd ← Rd XOR src

flags from Rd AND src
Rd is not written

n ← src & 15
if n ≠ 0: C ← bit (16 − n) of Rd; Rd ← (Rd << n) & FFFF

n ← src & 15
if n ≠ 0: C ← bit (n − 1) of Rd; Rd ← Rd >> n

n ← src & 15
if n ≠ 0: C ← bit (n − 1) of Rd; Rd ← s(Rd) >> n

n ← src & 15
if n ≠ 0: Rd ← (Rd << n | Rd >> (16 − n)) & FFFF; C ← bit 0 of Rd

p ← Rd × src (unsigned, 32-bit)
C ← 1 if p > FFFF
Rd ← p & FFFF

p ← s(Rd) × s(src) (signed, 32-bit)
q ← p >> 8 (arithmetic)
V ← 1 if q is outside −32768…32767
Rd ← q & FFFF

Rd ← sx8(imm8)

Rd ← Rd + sx8(imm8), flags as ADD

a ← effective address (see forms)
Rd ← mem16[a]

a ← effective address (see forms)
mem16[a] ← Rd

a ← effective address (see forms)
Rd ← mem8[a] (zero-extended)

a ← effective address (see forms)
mem8[a] ← Rd & 00FF

if condition: PC ← next + sx8(disp8) × 2

push(next)
PC ← next + sx8(disp8) × 2

PC ← addr

push(next)
PC ← addr

for r = 7 down to 0: if mask bit r = 1: push(Rr)

for r = 0 up to 7: if mask bit r = 1: Rr ← pop()

SP ← (SP + sx8(s8) × 2) & FFFF

PC ← mem16[(table + Rd × 2) & FFFF]

(none): a no-operation

2.16 Opcode map

Each cell is one value of the high byte (bits 15–8) of the first word; rows give bits 15–12 and columns bits 11–8. A cell lists every instruction whose first word has that high byte. Group 0 holds two operations per cell, because its operation field (bits 11–7) reaches one bit into the low byte; cell 0D holds SETF and a reserved operation, and cells 0E and 0F hold only reserved operations. Group 8 cells list LD, ST, LDB and STB, which differ only in bits 5–4. Group B has one operation per cell, as do groups 1, 2 and A; groups 3–9 carry a register number in bits 11–9, shown in small type. Hatched cells are reserved.

3 Reset, interrupts and system control

This chapter describes what the Tally processor does at power-on and reset, how the console refuses cartridges without a valid header, the vectors, the three hardware interrupts and the software trap, the programmable timer, and how the I/O registers behave under byte access. It ends with a complete list of undefined and reserved behaviour.

3.1 Power-on and reset

Power-on and the RESET button have the same effect. The processor and every I/O register are set to the following state:

In the reference model execution begins at dot 0 of line 0: the first instruction of the RESET routine starts at the first master cycle of the first frame.

The recommended start of every RESET routine is to load SP, disable the display, clear work RAM, VRAM, OAM and CRAM, then acknowledge any pending interrupt before enabling interrupts. §9.1 Reset and initialisation is a complete routine.

3.2 Cartridge lockout

At reset the console reads the four bytes at ROM 0010–0013. Unless they are the ASCII characters C, Y, C, L (43 59 43 4C), the processor is held in reset and never fetches an instruction; the display stays disabled. The lockout examines no other header field, and not the checksum. The other fields describe the cartridge rather than instruct the console: whether cartridge RAM answers at C000–DFFF is a property of the board itself, and header byte 0016 declares it. The reference model, which has no physical board to consult, fits cartridge RAM exactly when byte 0016 = 1 (§4.5 Cartridge RAM). The header is described in §4.4 The cartridge header.

3.3 Vectors

The vectors are words in ROM bank 0, which is always mapped at 0000:

Because the vectors and the handlers they point to must be reachable whatever bank is selected, keep every handler in bank 0.

3.4 Interrupts

Each source sets its bit in IF whenever its event happens, whether or not it is enabled. An interrupt is pending when its bit is set in both IE and IF. Bits 15–3 of IE and IF are not used.

The processor checks for interrupts between instructions, never inside one. At each check, if I = 1 and IE & IF ≠ 0 (and the check does not immediately follow EI, see below), it takes the highest-priority pending source:

push(PC)          ; the address of the instruction that would have run next
push(F)           ; F as it was, with I = 1
I ← 0
PC ← mem16[vector]

This sequence takes 12 cycles, plus the port wait cycles of its two pushes in the unlikely case that SP points at a video port. The stack then holds F at [SP] and the return address at [SP+2]. The handler ends with RTI, which pops F (restoring I = 1) and then PC.

Timing of entry. Interrupt entry is timed like an instruction: its two pushes take effect at the master-cycle time at which the entry starts, and any port wait they incur is judged at that time, exactly as for an instruction that starts at that boundary (§1.4 The reference timing model).

Events at a boundary. An event whose time equals an instruction boundary is processed before that boundary's interrupt check, so it can be taken there. The VBLANK request at dot 0 of line 224 always falls on a boundary: with I = 1 and IE bit 0 set, the interrupt is taken at that boundary, before the instruction that would otherwise have started there. A TIMER reload on the boundary behaves the same way.

Acknowledging. Taking an interrupt does not clear its IF bit. The handler must write a 1 to that bit of IF; writing 1 clears a bit and writing 0 leaves it unchanged, so ST R0,[IF] with R0 = 0001 acknowledges VBLANK only. A handler that returns without acknowledging is entered again immediately after its RTI.

Latency. An event that sets an IF bit while an instruction is executing is seen at the next instruction boundary. The worst case is therefore the longest instruction (or a DMA transfer, which belongs to the instruction that started it) plus the 12 entry cycles. WAI removes the uncertainty for a program with nothing else to do.

Nesting. Interrupts are disabled on entry. A handler that wants to allow a higher-priority interrupt acknowledges its own IF bit first, then executes EI; RTI restores the caller's I on the way out. Priority applies only when several sources are pending at the same check; a lower-priority source can interrupt a higher-priority handler that has re-enabled interrupts.

Polling. With a source disabled in IE, its IF bit may be polled and cleared by software; VSTAT bit 0 also shows vertical blank directly.

3.4.1 EI, DI and the one-instruction delay

DI clears I at once: no interrupt is taken at the boundary after it. EI sets I, but interrupts are not accepted at the boundary immediately after EI, only from the boundary after the following instruction. This makes two idioms safe:

        EI
        RTS             ; returns before any pending interrupt is taken

        EI
        WAI             ; sleep; the interrupt is taken as WAI completes

The delay applies every time EI executes, even when I is already 1: a pending interrupt is never taken at the boundary directly after an EI.

RTI and SETF load I directly, and the value they load applies from the next boundary.

3.4.2 TRAP

TRAP #n is a software interrupt. It is taken whatever the value of I and IE, and does not involve IF. It pushes the address of the next instruction and F, clears I, and jumps through the vector at 0008. The number n (0–15) is not used by the processor; a handler that dispatches on it reads the TRAP instruction word at (return address − 2) and takes bits 3–0.

3.5 WAI and STOP

WAI stops instruction fetch until an enabled interrupt is pending (IE & IF ≠ 0). Time passes normally while it waits: the video, audio, timer and controller sampling continue. WAI completes at the first CPU-cycle boundary at or after the moment IE & IF becomes non-zero. CPU-cycle boundaries are the master cycles that are multiples of 6 counted from power-on, so the processor never leaves the rhythm of its own clock. A LINE request, for example, is made at dot 256, 1024 master cycles into its line; 1024 is 4 past a boundary, so the wait ends 2 master cycles later, at 1026.

If I = 1 the interrupt is then taken, and RTI returns to the instruction after WAI. If I = 0 no interrupt is taken and the next instruction follows at once; the IF bit stays set for software to examine. A WAI with IE = 0 therefore waits forever. If an enabled interrupt is already pending when WAI is reached, WAI does not wait: with I = 1 the interrupt is taken before WAI executes (its RTI returns to the WAI itself), except directly after EI, when WAI executes first and the interrupt is taken at the boundary after it; with I = 0, WAI completes at once.

STOP halts only the processor, until reset. Nothing but reset restarts it; interrupts do not. The rest of the console carries on: the timer, video, audio and controller sampling keep running, and the interrupt sources go on setting their IF bits, although no interrupt is taken. Avenell's conformance cartridges end with STOP.

3.6 The programmable timer

The timer is a 16-bit down-counter driven by a prescaler that counts CPU cycles:

While the timer is enabled, the prescaler counts CPU cycles and every P cycles TCOUNT decrements. When TCOUNT would decrement from 0 it is instead loaded from TRELOAD and IF bit 2 is set. Any write to TCTRL resets the prescaler to the start of a period. The prescaler counts cycles whether the processor is executing, waiting in WAI or stopped by DMA.

So after writing TCOUNT = c and then TCTRL, the first TIMER request comes (c + 1) × P cycles later, measured from the start of the instruction that writes TCTRL (the time at which its write takes effect), and every following one (TRELOAD + 1) × P cycles after that. Examples:

3.7 Byte access to I/O registers

Every I/O register is 16 bits wide at an even address. Byte instructions may address either half:

• A byte read (LDB) of the register at a returns the low byte of the register's value; of a + 1, the high byte.
• A byte write (STB) writes that half and leaves the other half unchanged, except for the command registers described below.
• Side effects happen on byte accesses exactly as on word accesses. A byte read or write of VDATA advances VADDR by VINC; a byte read or write of OAMDATA advances OAMADDR by 2; a byte read or write of CRAMDATA advances CRAMADDR by 1; a byte read of VSTAT clears the sprite-overflow bit; a byte read of PROBE clears the ready bit.
• Command registers. DMACTL, V0CTRL–V3CTRL and IF hold no written value: a write is a command. They act on a word write, or on a byte write to their low byte (the even address), using the written low byte. A byte write to the high byte (odd address) is ignored.

Word accesses at an odd address are word accesses at the even address below, as everywhere else.

3.8 When register accesses take effect

The reference model applies every I/O register read and write made by an instruction at the master-cycle time at which that instruction starts, and processes timed events (line starts, interrupts, sampling) between instructions. An event due exactly at an instruction boundary is processed before that boundary's interrupt check (§3.4 Interrupts). A program that polls VCOUNT or writes scroll registers from a LINE handler sees and affects the hardware at instruction granularity. Rendering uses the register values present at dot 0 of each line (§5.8 The line pipeline: the dot-0 rule), so a write made during the horizontal blank of line y − 1 or earlier affects line y.

3.9 Undefined and reserved behaviour

The following list is complete. Behaviour not listed here is defined elsewhere in this manual.

4 Cartridges

A Cyclorama cartridge carries a ROM of one or more 16 KiB banks, a bank register and, on some boards, battery-backed RAM. The same bank-switching scheme serves every cartridge from the smallest to the largest.

4.1 ROM banks and the BANK register

The ROM is divided into 16 KiB banks numbered from 0. The processor sees two of them at a time: